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CD4514BC* CD4515BC 4-Bit Latched/4-to-16 Line Decoders
October 1987 Revised April 2002
CD4514BC* CD4515BC 4-Bit Latched/4-to-16 Line Decoders
General Description
The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are primarily used in decoding applications where low power dissipation and/or high noise immunity is required. The CD4514BC (output active high option) presents a logical "1" at the selected output, whereas the CD4515BC presents a logical "0" at the selected output. The input latches are R-S type flip-flops, which hold the last input data presented prior to the strobe transition from "1" to "0". This input data is decoded and the corresponding output is activated. An output inhibit line is also available.
Features
s Wide supply voltage range: s Low power TTL: fan out of 2 compatibility: driving 74L s Low quiescent power dissipation: 0.025 W/package @ 5.0 VDC s Single supply operation s Input impedance = 1012 typically s Plug-in replacement for MC14514, MC14515 3.0V to 15V s High noise immunity: 0.45 VDD (typ.)
Ordering Code:
Order Number CD4514BCWM CD4514BCN CD4515BCWM CD4515BCN Package Number M24B N24A M24B N24A Package Diagram 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600" Wide 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Top View
(c) 2002 Fairchild Semiconductor Corporation
DS005994
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CD4514BC* CD4515BC
Truth Table
Decode Truth Table (Strobe = 1) Data Inputs Inhibit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
X = Don't Care
Selected Output A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X CD4514 = Logic "1" CD4515 = Logic "0" S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 All Outputs = 0, CD4514 All Outputs = 1, CD4515
D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X
C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X
B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X
Logic Diagram
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CD4514BC* CD4515BC
Absolute Maximum Ratings(Note 1)
(Note 2) DC Supply Voltage (VDD ) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) 260C 700 mW 500 mW
Recommended Operating Conditions (Note 2)
DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4514BC, CD4515BC 3V to 15V 0V to VDD
-0.5V to +18V -0.5V to VDD + 0.5V -65C to +150C
-55C to +125C
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electrical Characteristics" provide conditions for actual device operation. Note 2: VSS = 0V unless otherwise specified.
DC Electrical Characteristics (Note 2)
CD4514BC, CD4515BC Symbol IDD Parameter Quiescent Device Current VOL LOW Level Output Voltage Conditions VDD = 5V, VIN = VDD or V SS VDD = 10V, VIN = VDD or V SS VDD = 15V, VIN = VDD or V SS VIL = 0V, VIH = VDD, |IO| < 1 A VDD = 5V VDD = 10V VDD = 15V VOH HIGH Level Output Voltage VIL = 0V, VIH = VDD, |IO| < 1 A VDD = 5V VDD = 10V VDD = 15V VIL LOW Level Input Voltage |IO| < 1 A VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V VIH HIGH Level Input Voltage |IO| < 1 A VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V IOL LOW Level Output Current (Note 3) IOH HIGH Level Output Current (Note 3) IIN Input Current VDD = 5V, VO = 0.4V VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V VDD = 5V, VO = 4.6V VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V
Note 3: IOH and IOL are tested one output at a time.
-55C Min Max 5 10 20 Min
+25C Typ 0.005 0.010 0.015 Max 5 10 20
+125C Min Max 150 300 600
Units
A
0.05 0.05 0.05
0 0 0
0.05 0.05 0.05
0.05 0.05 0.05 V
4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.64 1.6 4.2 -0.64 -1.6 -4.2 -0.1 0.1
4.95 9.95 14.95
5.0 10.0 15.0 2.25 4.50 6.75 1.5 3.0 4.0
4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.36 0.90 2.4 -0.36 -0.90 -2.4 -0.1 0.1 -1.0 1.0 A mA mA V V V
3.5 7.0 11.0 0.51 1.3 3.4 -0.51 -1.3 -3.4
2.75 5.50 8.25 0.88 2.25 8.8 -0.88 -2.25 -8.8 -10-5 10-5
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CD4514BC* CD4515BC
AC Electrical Characteristics
Symbol tTHL, tTLH Parameter Transition Times
(Note 4)
Conditions Min Typ 100 50 40 550 225 150 400 150 100 125 50 38 175 50 38 150 5 7.5 Max 200 100 80 1100 450 300 800 300 200 250 100 75 350 100 75 pF pF ns ns ns ns ns Units
All types CL = 50 pF, TA = 25C, tr = tf = 20 ns unless otherwise specified VDD = 5V VDD = 10V VDD = 15V tPLH, tPHL Propagation Delay Times VDD = 5V VDD = 10V VDD = 15V tPLH, tPHL Inhibit Propagation Delay Times tSU Setup Time VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V tWH Strobe Pulse Width VDD = 5V VDD = 10V VDD = 15V CPD CIN Power Dissipation Capacitance Input Capacitance Per Package (Note 5) Any Input (Note 6)
Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note, AN-90. Note 6: Capacitance is guaranteed by periodic testing.
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CD4514BC* CD4515BC
AC Test Circuit and Switching Time Waveforms
FIGURE 1.
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CD4514BC* CD4515BC
Applications
Two CD4512 8-channel data selectors are used here with the CD4514B 4-bit latch/decoder to effect a complex data routing system. A total of 16 inputs from data registers are selected and transferred via a 3-STATE data bus to a data distributor for rearrangement and entry into 16 output registers. In this way sequential data can be re-routed or intermixed according to patterns determined by data select and distribution inputs. Data is placed into the routing scheme via the 8 inputs on both CD4512 data selectors. One register is assigned to each input. The signals on A0, A1 and A2 choose 1-of-8 inputs for transfer out to the 3-STATE data bus. A fourth signal, labelled Dis, disables one of the CD4512 selectors, assuring transfer of data from only one register. In addition to a choice of input registers, 1-16, the rate of transfer of the sequential information can also be varied. That is, if the CD4512 were addressed at a rate that is 8 times faster than the shift frequency of the input registers, the most significant bit (MSB) from each register could be selected for transfer to the data bus. Therefore, all of the most significant bits from all of the registers can be transferred to the data bus before the next most significant bit is presented for transfer by the input registers. Information from the 3-STATE bus is redistributed by the CD4514B 4-bit latch/decoder. Using the 4-bit address, INA-IND, the information on the inhibit line can be transferred to the addressed output line to the desired output registers, A-P. This distribution of data bits to the output registers can be made in many complex patterns. For example, all of the most significant bits from the input registers can be routed into output register A, all of the next most significant bits into register B, etc. In this way horizontal, vertical, or other methods of data slicing can be implemented.
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CD4514BC* CD4515BC
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B
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CD4514BC* CD4515BC 4-Bit Latched/4-to-16 Line Decoders
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600" Wide Package Number N24A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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